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CDB8422
2.2
2.2.1
Configuration Options
In software mode, to configure the CDB8422 for making performance measurements, one needs to use Cir-
rus Logic’s Windows compatible FlexGUI software to program the various components on the board. This
section serves to give a deeper understanding of the on-board circuitry and the digital clock and data signal
routing involved in several common software mode configurations of the CDB8422. These scripts only serve
as a starting point; after loading a script, the GUI can be further configured as needed (clock ratios, serial
formats, etc).
S/PDIF In to S/PDIF and PCM Out
The CS8422’s S/PDIF receiver and SRC output performance can be tested by loading the “SPDIF In to
SPDIF and PCM Out” quick setup file provided with the software package. The script configures the dig-
ital clock and data signal routing on the board as shown in Figure 2 .
Digital S/PDIF input can be provided on the optical (J1) or RCA (J7) jacks. Jumper J4 selects which input
signal is connected to the RX0 pin of the CS8422. The script configures the CS8422’s internal circuitry to
send the input audio data through its SRC to serial output port 1. This data is presented as PCM audio at
header J24 and S/PDIF audio at J27 (coaxial) and J28 (optical). The input data is also passed through
(SRC is bypassed) to serial output port 2. This data is presented as PCM audio at header J25. Refer to
Section 2.3 for details on software configuration.
Header
J24
OSCLK1
OLRCK1
SDOUT1
MCLK OUT
PCM Out
through SRC
Optical
Buffer
Buffer
CS8406
S/PDIF Tx
J28
S/PDIF
Out
Optical
S/PDIF In
J1
OSCLK1
(MASTER) OLRCK1
SDOUT1
ISCLK
ILRCK (SLAVE)
SDIN
S/PDIF
OUT
J31
AND
OMCK
Coaxial
OR
J4
RX0
CS8422
RMCK
Buffer
Header
J25
J27
S/PDIF
Out
Coaxial
S/PDIF In
J7
OSCLK2
MCLK OUT
OSCLK2
PCM Out
no SRC
(MASTER) OLRCK2
SDOUT2
OLRCK2
SDOUT2
Figure 2. S/PDIF In to S/PDIF and PCM Out
DS692DB2
7
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